1. Field of the Invention
This invention relates to a semiconductor device and manufacturing method therefor, and particularly to technology useful for easily effecting high functionality in semiconductor devices comprising a semiconductor element or elements (chip or chips) mounted in a package.
2. Description of the Related Art
Various forms have been proposed for semiconductor devices constituted by mounting a semiconductor element or elements in a package. One example thereof is a semiconductor device wherein a plurality of semiconductor chips is mounted on one substrate to achieve higher integration and higher functionality.
Specific forms of such a semiconductor device which are known include, for example, those wherein semiconductor chips are mounted respectively on both sides of the substrate, those wherein semiconductor chips are stacked on one side of the substrate, and those wherein a plurality of semiconductor chips is mounted inside the surfaces of the substrate.
In every one of these forms, a wiring pattern is suitably formed on the surface of the substrate, to which wiring patterns the electrode pads (terminals) of the semiconductor chips are electrically connected by wire bonding.
Of course, the electrical connections between the semiconductor chips and the wiring patterns are not limited to wire bonding connections, and flip chip connections and TAB connections and the like can also be used.
In the conventional semiconductor devices described above, because the semiconductor chips are mounted on the substrate mounting surface, the fact that substrates are made in prescribed sizes means that the number of semiconductor chips that can be mounted is limited, which is a disadvantage.
Also, when semiconductor chips are mounted in a stack, it is necessary to make the upper chips smaller in size than the lower chips by an amount equal to the area which is needed to make the wire bonding connections. Hence the mounting area of the upper chip or chips becomes narrow, and there is inherently a limit to the number of chips that can be stacked up.
In this case, when flip chip connections are used, there is no need to provide room for bonding as described above, for which reason, it is possible to increase the number of chip mountings compared to when wire bonding connections are used, but other difficulties arise.
In general, with flip chip mounting, bumps (electrode terminals) made of solder or other metals are formed on the electrode pads of the semiconductor chips, and connections are effected by thermally pressing these bumps down on top of corresponding electrode pads on the printed circuit board or other mounting substrates.
When this approach is applied to layered forms of chips, the upper chip will be flip-chip connected to the lower chip.
In such cases, it is necessary to form electrode pads on the upper surface of the lower chip in such a way that they correspond to the positions of the bumps that are the electrode terminals of the upper chip. Furthermore, when the chips are stacked, the positions of the bumps on the upper chips and the electrode pads on the lower chips must be aligned, resulting in the disadvantage that the overall process becomes complex.
In such a conventional semiconductor device as this, because the semiconductor chips are simply mounted on the mounting surface of the substrate, the number of semiconductor chips mounted is limited, and it is not always possible to realize adequately high functionality or the like, which is a problem.
Also, because the semiconductor chips are mounted in a form in which they are externally attached to the substrate, another disadvantage arises in that the overall semiconductor device becomes relatively thick.
Meanwhile, semiconductor device designs which are different from those of the conventional form described in the foregoing, have been conceived in which the substrate is made multi-layered and the semiconductor chips are placed inside the substrate, in order to achieve even higher integration and higher functionality.
For example, if a multi-layer substrate structure is used which is provided with a plurality of wiring layers, it is possible to electrically interconnect the semiconductor chips and place them three-dimensionally inside the substrate.
However, not only is it not necessarily easy to implant semiconductor chips inside a substrate and form the wiring layers as multiple layers but when consideration is given to the recent demand for packages to be smaller and lighter in weight, there is the problem of having to reduce the overall thickness and make the semiconductor device more compact.
An object of the present invention, which has been devised in view of the problems in the prior art described in the foregoing, is to provide a semiconductor device with which it is possible to effect a compact configuration when mounting semiconductor elements in a package, with which, as necessary, the three-dimensional arrangement and configuration of the semiconductor elements and the interconnections therebetween can be easily implemented, and which contributes to achieving even higher functionality, and to provide a manufacturing method therefor.
Specifically, the present invention is as follows.
1. A semiconductor device comprising: a wiring substrate, wherein conductor layers having wiring patterns formed on them, are formed on both surfaces thereof, with an insulating layer intervening therebetween, and protective films are formed to cover the wiring patterns and the insulating layer in such a way that terminal formation portions of the wiring patterns to which external connection terminals are to be connected are exposed; and at least one semiconductor element that is mounted and imbedded in that wiring substrate; wherein electrode terminals of the semiconductor element are electrically connected to both wiring patterns on both the surfaces.
2. A semiconductor device comprising: a wiring substrate, wherein a conductor layer having a wiring pattern formed on it, is formed on an insulating layer, and a protective film is formed to cover the wiring pattern and the insulating layer in such a way that terminal formation portions of the wiring pattern to which external connection terminals are to be connected are exposed; and at least one semiconductor element that is mounted and imbedded in that wiring substrate; wherein electrode terminals of the semiconductor element are electrically connected to the wiring pattern.
3. A semiconductor device comprising two or more of the semiconductor devices cited in 1 above, stacked in such a way that they are electrically connected.
4. A stacked semiconductor device comprising one or more of the semiconductor devices cited in 1 above and the semiconductor device cited in 2 above, stacked in such a way that they are electrically connected.
5. The semiconductor device according to claim 1 above, wherein the thickness of the semiconductor element is 100 xcexcm or less.
6. A semiconductor device manufacturing method comprising: a first step for mounting, in a base substrate which comprises a first insulating layer with a first conductor layer comprising a wiring pattern on one surface side thereof, a requisite number of semiconductor elements on the other surface side of the first insulating layer; a second step for forming a second insulating layer so as to cover the semiconductor elements, and forming a second conductor layer comprising a wiring pattern on the second insulating layer; a third step for forming via holes at certain positions in the second conductor layer so as to reach the electrode terminals of the semiconductor elements and for also forming through holes at positions that avoid portions where the semiconductor elements are imbedded, so as to pass completely through in the up-and-down direction; a fourth step for forming a third conductor layer over the entire surface inclusive of the inner wall surfaces of the via holes and through holes; a fifth step for forming a wiring pattern, by effecting patterning, on the third conductor layer, in such a way that electrode terminals of the semiconductor elements are electrically connected to the second conductor layer via conductor layers on the inner wall surfaces of the via holes and also in such a way that the second conductor layer is electrically connected to the first conductor layer via conductor layers on the inner wall surfaces of the through holes; a sixth step for obtaining a structure by forming a protective film covering the wiring patterns and the first and second insulating layers in such a way that the terminal formation portions of the wiring pattern of the third conductor layer to which external connection terminals are to be connected are exposed; and a seventh step for dividing the structure obtained by the sixth step into semiconductor devices in such a way that at least one semiconductor element is contained in each semiconductor device.
7. The semiconductor device manufacturing method according to 6 above, comprising a step for forming external connection terminals comprising metal bumps for the terminal formation portions of the wiring pattern on the third conductor layer, after the sixth step.
8. A semiconductor device manufacturing method comprising: a step I for mounting a requisite number of semiconductor elements on a base substrate; a step II for forming an insulating layer so as to cover the semiconductor elements and the base substrate; a step III for forming via holes at certain positions in the insulating layer in such a way that they extend to the electrode terminals of the semiconductor elements; a step IV for forming a conductor layer on the insulating layer, filling in the via holes, and for effecting patterning to form a wiring pattern; a step V for obtaining a structure, forming a protective film that covers the wiring pattern and the insulating layer in such a way that terminal formation portions of the wiring pattern to which external connection terminals are to be connected are exposed; a step VI for dividing the structure obtained by step V into semiconductor devices in such a way that at least one semiconductor element is contained in each semiconductor device; and a step VII for stacking the semiconductor devices fabricated in this manner in such a way that electrical connection is effected with semiconductor device cited in 1 above.
9. The semiconductor device manufacturing method according to 8 above, comprising a step for forming external connection terminals comprising metal bumps at terminal formation portions of the wiring pattern, after the step V.
According to the semiconductor device relating to 1 above and the manufacturing method relating to 6 above, which constitute a first embodiment aspect of the present invention, semiconductor elements are imbedded/mounted inside a wiring substrate provided as a package, with the result that the semiconductor device can be configured compactly.
Also, because provision is made to the effect that the terminal formation portions of the wiring patterns on both side surfaces of the wiring substrate (package) are exposed out of the protective film, and to the effect that, as necessary, multi-level stacking-up can be effected, three-dimensional structuring of the semiconductor elements and interconnections therebetween can be effected simply with the external connection terminals intervening therebetween, as in the semiconductor device described in 3 above. Thus it is possible to realize higher functionality in the semiconductor device.
Furthermore, according to the semiconductor device relating to 2 above, which is a second embodiment aspect of the present invention, the semiconductor elements are imbedded/mounted inside the wiring substrate as in the first form described in the foregoing, as a result of which the semiconductor device can be configured compactly.
Also, by stacking this semiconductor device while electrically connecting it to the semiconductor device relating to 1 above, as in 4 above, it is possible to effect higher functionality in the semiconductor device.
The reason why division into the semiconductor devices is made in the seventh step in 6 above, moreover, is that, when a structure is obtained in which these semiconductor devices are connected together, in the sixth step, it is necessary to separate off each semiconductor device. The situation is the same in step VI in 8 above.